rtl register transfer level us

completed70 qualified1 runMar 30, 8:34 AMrtl-register-transfer-level-us

Qualified Candidates (54)

Ahmed Agiza

high hireability

Machine Learning Research Scientist@Meta

Previously: Graduate Research Assistant @ Brown University

San Francisco, US

Top-tier RTL/EDA experience: deep OpenROAD contributor (160 commits, RTL-to-GDS), OpenPhySyn co-author (EDA physical synthesis, Verilog), and NVIDIA EDA ML work
PhD specialization at ML+hardware intersection
US-based
Hireability elevated by confirmed large-scale Meta layoffs in March 2026

OpenPhySyn: An Open-Source Physical Synthesis Optimization Toolkit GraPhSyM: Graph Physical Synthesis Model The-OpenROAD-Project/OpenROAD scale-lab/OpenPhySyn ahmed-agiza/EDAViewer

Andrew Nolte

high hireability

Qualified: US-based (New York) RTL engineer at Hudson River Trading writing SystemVerilog for FPGA/ASIC
Direct contributor to verilator (24 commits), open-sourced HRT's slang-server language server, maintains vscode-system-verilog
Top-tier RTL tooling contributor
Not a professor, not a founder

hudson-trading/slang-server AndrewNolte/vscode-system-verilog verilator/verilator

Eren Dogan

high hireability

Strong match: active OpenROAD contributor (RTL-to-GDS), FPGA project, SystemVerilog coursework, Chisel hardware generator, and deep VLSI/EDA research background
Fourth-year PhD at UCSC VLSIDA lab — high hireability
Website CV update in Oct 2025 confirms career motion
US-based
Qualifies as top-1% RTL/EDA candidate

Effective Capacitance Modeling Using Graph Neural Networks GAT-Steiner: Rectilinear Steiner Minimal Tree Prediction Using GNNs (ICCAD 2024)VLSI Hypergraph Partitioning with Deep Learning (MLCAD 2024)erendn/sobel-pipeline-fpga erendn/chisel-image-processor The-OpenROAD-Project/OpenROAD

John Coiner

high hireability

US-based industry engineer with deep RTL tooling expertise
Authored multi-threaded execution mode in Verilator — directly relevant to Verilog/RTL simulation infrastructure
Long AMD background strongly implies hands-on RTL design experience
Not a professor, founder, or sole proprietor

verilator/verilator (36 commits — multi-threaded execution mode author)jcoiner/memtest

John Wright

high hireability

Passes all hard rejection rules
Senior ASIC Design Engineer at Amazon Lab126 (not a professor, founder, or consultant)
US-based in Oakland, CA
Core contributor to major open-source RTL/Chisel ecosystems (Chipyard, Rocket Chip, Hammer EDA)
Led full SoC RTL projects at Berkeley
Exactly the top-1% RTL/ASIC profile the search targets

Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs (IEEE Micro 2020)ucb-bar/chipyard ucb-bar/hammer ucb-bar/chisel-awl ucb-bar/barstools chipsalliance/chisel

Kamyar Mohajerani

high hireability

Strong RTL signal across Bluespec SystemVerilog/VHDL/Chisel/Verilog with focus on cryptographic hardware (FPGA + ASIC)
PhD defended July 2025 from one of the top cryptographic hardware labs in the US (GMU CERG)
Currently Senior Engineer at Quest Global (Performance Modeling for Meta Reality Labs, Remote)
US-based (Fairfax, VA)
Not a professor, founder, or consultant
Top-1% qualifier for this search

High-Speed Hardware Architectures and Fair FPGA Benchmarking of CRYSTALS-Kyber, NTRU, and Saber FPGA Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST LWC Process A High-Performance Hardware Implementation of the LESS Digital Signature Scheme Efficient and Secure Hardware Implementation of Cryptographic Algorithms (PhD thesis, July 2025)bluelight kyber.light sparkle XedaHQ/xeda chisel.g8

Kevin Laeufer

high hireability

Top-1% RTL candidate
Entire research career is squarely on RTL design, automated hardware testing, and hardware construction languages (Chisel/FIRRTL). 59 commits to chipsalliance/chisel
Pinned repos include rfuzz (coverage-directed RTL fuzzing on FPGAs), rtl-repair (symbolic repair of hardware code), simulator-independent-coverage, and wellen (waveform tooling)
Published at ASPLOS x3 (2023, 2024), CAV 2025, ICCAD 2018
Co-designed ChiselTest and ChiselVerify
US-based (Ithaca, NY)
Hireability: HIGH — completed PhD from UC Berkeley in 2024, now Research Associate + Visiting Lecturer at Cornell (Capra group) since Aug 2024 (~1.5 years in). Postdoc-equivalent in years 1-3 window = HIGH per matrix. Still actively committing (latest commit March 12, 2026)

RTL-Repair: Fast Symbolic Repair of Hardware Design Code Simulator Independent Coverage for RTL Hardware Languages RFUZZ: Coverage-Directed Fuzz Testing of RTL on FPGAs ekiwi/rfuzz ekiwi/rtl-repair ekiwi/simulator-independent-coverage

Aditya Naik

medium hireability

Qualified: Strong RTL topic match (Chisel/FIRRTL/CIRCT/Rocket Chip) + Medium hireability maps to Qualify per decision matrix
US-based (San Francisco, CA), no hard disqualifiers

adkian-sifive/sfc-scala3 adkian-sifive/firrtl-ebnf chipsalliance/chisel

Albert Magyar

medium hireability

Strong RTL/Chisel/FIRRTL expertise — core contributor to foundational Berkeley hardware design tools with 198 commits to chipsalliance/chisel
Co-authored seminal FIRRTL paper, Chipyard, FireSim, Golden Gate
US-based (California)
Top 1% RTL candidate
Hireability is medium: currently a Software Engineer at Google (post-PhD), no active job-seeking signals, but within a plausible transition window given ~4 years tenure

Reusability is FIRRTL Ground: Hardware Construction Languages, Compiler Frameworks, and Transformations Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes albert-magyar/vscale chipsalliance/chisel firesim/firesim

Alphan Ulusoy

medium hireability

914 commits to lowRISC/opentitan (rank #6 contributor), a premier open-source silicon root of trust written in SystemVerilog — direct and substantial RTL design/verification work
Prior RTL background at Vestek R&D (2008-2010) doing IC design/verification of video enhancement chips
US-based (Framingham, MA)
Hireability: MEDIUM — currently Senior SWE at Google with no explicit job-seeking signals, but deep continued engagement in open-source RTL suggests hardware passion that may outpace his SWE role; worth reaching out

lowRISC/opentitan lowRISC/ot-sca

Amelia Dobis

medium hireability

Qualified: PhD student (not professor, not founder) with exceptional hands-on RTL/hardware verification depth
US-based at Princeton
Former SiFive compiler engineer building Chisel/CIRCT verification tools
Core contributor to chipsalliance/chisel, llvm/circt, and chiselverify
Medium hireability due to early-stage PhD (~year 1-2) with no near-term graduation signals

Formally Verifying Arithmetic Chisel Designs for All Bit Widths at Once (DAC 2024)Incremental Conversion of SVA Properties to Synthesizable Hardware (LATTE 2025)Formal Verification of Hardware using MLIR (ETH MSc Thesis, April 2024)Verification of Chisel Hardware Designs with ChiselVerify ChiselVerify: An Open-Source Hardware Verification Library for Chisel and Scala llvm/circt chipsalliance/chisel chiselverify/chiselverify dobios/btor2-opt

Bing-Yue Wu

medium hireability

Moderate-to-Strong RTL/EDA relevance (OpenROAD RTL-to-GDS contributor, Verilog primary language on forked repo, physical design publications) + Medium hireability (early-mid PhD, CV recently updated)
Meets qualify threshold per decision matrix

OpenROAD-Assistant: An Open-Source Large Language Model for Physical Design Tasks OpenROAD Agent: An Intelligent Self-Correcting Script Generator for OpenROAD (ICLAD 2025)DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Design (ASP-DAC 2026)The-OpenROAD-Project/OpenROAD bingyuew/OpenROAD bingyuew/OpenSTA

David Biancolin

medium hireability

Co-creator of FireSim and lead developer of Golden Gate (MIDAS II), the optimizing FPGA-accelerated RTL simulation compiler (ICCAD 2019)
Active Chisel contributor (26 commits, Dec 2024 merged PR fixing ModuleChoice under D/I)
PhD EECS Berkeley 2021; Senior Staff Engineer @SiFive, Berkeley CA
Hireability: MEDIUM — ~4 years at SiFive (in transition window), no explicit open-to-work signals, but SiFive structural instability is a positive outreach factor

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud (ISCA 2018)Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes (ICCAD 2019)FASED: FPGA-Accelerated Simulation and Evaluation of DRAM (FPGA 2019)DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles (FPL 2018)Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim (IEEE Micro 2021)Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs (IEEE Micro 2020)Simulator Independent Coverage for RTL Hardware Languages (ASPLOS 2023)Evaluation of RISC-V RTL with FPGA-Accelerated Simulation (CARRV 2017)firesim/firesim ucb-bar/chipyard chipsalliance/chisel

Drew Lewis

medium hireability

Strong RTL/EDA signal: 20 commits to OpenROAD covering build infrastructure, ABC integration, performance, and correctness fixes
Forks of Yosys, ABC, and OpenSTA confirm broad EDA toolchain engagement
US-based (Roanoke, VA)
Senior SWE at Google actively contributing to open-source RTL/EDA tools as recently as Feb 2026
Qualifies as top-tier RTL/EDA talent

The-OpenROAD-Project/OpenROAD calewis/yosys calewis/abc calewis/OpenSTA

Ethan Mahintorabi

medium hireability

415 contributions to OpenROAD (RTL-to-GDS EDA tool), pinned HDL/Verilog repos, published ASIC workflow research, mentors on LEF parsing and chip design tooling at Google
Squarely in the top 1% of RTL/EDA contributors
US-based (Seattle)
Hireability medium — currently at Google with no open-to-work signal

Software Inspired IC Hardware Workflows Using Bazel The-OpenROAD-Project/OpenROAD hdl/bazel_rules_hdl

Ethan Sifferman

medium hireability

Qualified: US-based (California) PhD student with deep synthesizable Verilog/SystemVerilog RTL expertise, open-source silicon contributions (Verilator, SKY130, yosys, CVA6), and FPGA/ASIC tool experience
Not a professor, founder, or consultant
Strong top-1%-for-level signal for a PhD student

Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders (Master's Thesis)sky130_schematics labs-with-cva6 verilog_template vivado_acorn

Fabian Schuiki

medium hireability

Strong match on all technical dimensions: CIRCT core contributor, LLHD creator, hardware compiler engineer with PhD in Computer Architecture, active in chipsalliance/chisel ecosystem
US-based (Silicon Valley, CA)
Qualifies under Strong+Medium → Qualify rule. ~5yr tenure at SiFive introduces some friction but no hard disqualifier

LLHD: A Multi-level Intermediate Representation for Hardware Description Languages llhd moore

Felipe Garay

medium hireability

Felipe is a top-tier RTL/EDA engineer at Google contributing directly to OpenROAD's DFT infrastructure — scan insertion, scan optimization, scandef support
This is highly specialized RTL design toolchain work (not just usage but core tool development)
US-based in Mountain View, CA
Qualifies as top 1% in RTL/EDA domain

The-OpenROAD-Project/OpenROAD fgaray/OpenROAD

Girish Pai

medium hireability

Qualified: Strong RTL/verification signal — Principal Engineer at SiFive with 6+ years, deep SystemVerilog/UVM expertise, 4 core-language Chisel commits to chipsalliance/chisel, ASIC background from TI/Wipro/Marvell
US-based (San Jose, CA) confirmed
Hireability medium due to active senior SiFive employment with no open-to-work signal

chipsalliance/chisel

Glen Gibb

medium hireability

World-class RTL/hardware design credentials: Stanford PhD (EE, 2013) on 'Reconfigurable Hardware for Software-Defined Networks', co-designed the RMT (Reconfigurable Match Tables) architecture that became the foundation of P4 and Tofino chips
At Barefoot Networks, designed programmable packet parsers in RTL for multiple Tofino chip generations and built RTL generation infrastructure (synthesizable Verilog parser generator)
Contributed to Verilator
Based in St Louis, MO (US)
Hireability: MEDIUM — currently at a stealth startup as Software Engineer Lead; unclear tenure, no explicit open-to-work signals, but employer opacity and small company size suggests potential openness to the right opportunity

Reconfigurable Hardware for Software-Defined Networks (PhD Dissertation)Design Principles for Packet Parsers (ANCS 2013)verilator/verilator grg/parser-gen grg/Genesis2

Hideto Ueno

medium hireability

Core contributor to LLVM/CIRCT (Chisel-to-RTL compiler toolchain) at SiFive, the birthplace of RISC-V and Chisel
Deep expertise in RTL tooling, FIRRTL, Verilog export, synthesis optimization, and hardware compiler infrastructure
US-based (Milpitas, CA)
Active 2025 CIRCT contributions confirmed
Top-1% match for RTL/Chisel/RISC-V search

llvm/circt sifive/chisel-circt chipsalliance/chisel

Kaleb Barrett

medium hireability

FPGA Verification Engineer at Hudson River Trading; core maintainer of cocotb (Python-based RTL/chip verification framework) with deep contributions to verilator; prior Principal FPGA Engineer at Raytheon/Mercury Systems with VHDL chip design experience
Top-tier RTL verification profile — actively building tooling at the intersection of hardware design and software automation
Hireability: MEDIUM — no explicit 'open to work' signals, website activity is personal blog only (no CV updates), but tenure at HRT likely 3-5+ years and within a plausible transition window

cocotb/cocotb verilator/verilator ktbarrett/coconext

Matthew Ballance

medium hireability

US-based (Portland, OR), at AMD, not a professor or founder
Long career in EDA and hardware verification with demonstrated SystemVerilog/Verilog RTL skills (FWRISC RISC-V core, Verilator contributor, sveditor)
Top of field for verification methodology

Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor fvutils/pyvsc — Python Verification Stimulus and Coverage sveditor/sveditor — SystemVerilog Development Environment fvutils/pyhdl-if — Python interface for cross-calling with HDL fvutils/pyucis — Python API to UCIS Coverage Data mballance/tt-demo — TL-Verilog demo (Tiny Tapeout)

Megan Wachs

medium hireability

Strong relevance + Medium hireability per decision matrix → Qualify
Top-1% RTL/RISC-V/Chisel credentials (PhD Stanford EE, pioneering SiFive RTL engineer, RISC-V Debug Task Group chair, 89 chisel contributions)
US-based (San Francisco, CA)
Hireability upgraded from LOW to MEDIUM: web search confirms she has left SiFive VP role and moved to Silicon Labs/MIPS, indicating recent career mobility

chipsalliance/rocket-chip sifive/sifive-blocks sifive/freedom

Michael Maloney

medium hireability

Industry RTL/Chisel engineer at SiFive contributing to upstream Chisel language features
US-based
Not a professor, founder, or consultant

chipsalliance/chisel (contributor — Add withModulePrefix feature)mmaloney-sf/firrtlizer mmaloney-sf/tree-sitter-firrtl (fork)

Michael Popoloski

medium hireability

Creator and primary maintainer of 'slang' — the fastest and most compliant open-source SystemVerilog compiler and language services library (used in synthesis tools, simulators, linters); also created pyslang (Python bindings) and contributed to verilator
Core developer at Hudson River Trading working on FPGA and high-performance hardware in the US
BE/ME in Computer Engineering from Stevens Institute of Technology
This is top-1% RTL toolchain work — building the compiler infrastructure that the entire SystemVerilog ecosystem depends on
Hireability: MEDIUM — long-tenure core developer at HRT (5+ years likely), but actively committing to slang as recently as 2026-03-25, suggesting continued engagement; no explicit open-to-work signals found

MikePopoloski/slang MikePopoloski/pyslang verilator/verilator

Mike Inouye

medium hireability

52 commits to The-OpenROAD-Project/OpenROAD (RTL-to-GDS EDA flow written in Verilog), with pinned forks of the full open-source silicon stack: Yosys (synthesis), OpenSTA (static timing analysis), and ABC (logic synthesis/formal verification)
This is the canonical open-source chip design toolchain — forking and contributing to all four repos signals deep, active RTL/EDA engineering
Confirmed US-based (Sunnyvale, CA)
Hireability: MEDIUM — currently at Google, no open-to-work signal, no bio text, latest commit email dated 2021 (activity may have slowed); but top-1% domain fit for RTL/EDA warrants outreach

The-OpenROAD-Project/OpenROAD mikesinouye/yosys mikesinouye/OpenSTA

Mingyu Woo

medium hireability

Main developer of OpenROAD (DARPA-POSH), an open-source RTL-to-GDS EDA flow — authored global placement (RePlAce) and detailed placement (OpenDP) tools; 144 commits to The-OpenROAD-Project/OpenROAD; all three pinned repos are Verilog/RTL-to-GDS toolchain projects; PhD from UCSD ABK Group, one of the top VLSI CAD research groups globally
Focus is VLSI physical design (EDA tooling, floorplan/placement) rather than front-end RTL logic design in Verilog/SystemVerilog, but deep hands-on expertise in the RTL-to-GDS flow makes him highly relevant to chip design teams building or scaling ASIC/FPGA infrastructure
US-based (San Diego, CA)
Hireability: MEDIUM — ~3 years into a Senior Engineer role at Qualcomm (joined ~April 2023); within the 2-4 year transition window; no explicit open-to-work signals (GitHub Pages dormant last 180 days, no LinkedIn change signals detected); tenure short enough that outreach is worth attempting

The-OpenROAD-Project/OpenROAD The-OpenROAD-Project/RePlAce The-OpenROAD-Project/OpenROAD-flow-scripts

Noah Moroze

medium hireability

Strong RTL pedigree: authored lemoncore (RISC-V processor in Verilog for FPGAs), zerosoc (SystemVerilog demo SoC), contributed to SiliconCompiler (open-source EDA build system) and OpenROAD (RTL-to-GDS flow, 12 commits), and built Switchboard (RTL simulation/emulation communication framework)
MIT EECS BS + MEng (thesis: formal verification of SoC security properties using Rosette)
Based in San Francisco, US
Hireability: MEDIUM — website updated 2025-11-03 confirming move to Waymo as ML compiler engineer on compute team; ~5 months into the role (recent hire). Current role is not RTL/hardware, which may create motivation to return to silicon, but he just started so outreach should be gentle

nmoroze/lemoncore siliconcompiler/zerosoc zeroasiccorp/switchboard

Ryan Ridley

medium hireability

Strong RTL/ASIC signal: SystemVerilog design work, active OpenROAD contributor (10 commits), SkyWater PDK familiarity
US-based at NASA Goddard (Maryland)
Qualifies on Strong relevance + Medium hireability per decision matrix

rjridle/Divider_Radix1 The-OpenROAD-Project/OpenROAD rjridle/skywater-pdk

Schuyler Eldridge

medium hireability

Strong match: core contributor to Chisel (1,262 commits), active on CIRCT (hardware IR compiler), co-author of FIRRTL spec, RISC-V accelerator builder, PhD-level hardware compiler expertise
Matches all top-1% RTL keywords (RTL, hardware compiler, RISC-V, ASIC, Chisel)
US-based in New York, NY
Hireability medium due to 5+ year tenure at SiFive with no detected open-to-work signals

Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems Building Loosely-coupled RISC-V Accelerators using Chisel/FIRRTL chipsalliance/chisel llvm/circt chipsalliance/firrtl-spec

Tim Snyder

medium hireability

Elite RTL/hardware design career: Senior Design Engineer at AMD, Staff Engineer of Logic Design at Samsung SARC/ACL (multiple stints at Principal level), Principal Engineer at SiFive (RISC-V chip design), and currently Senior Principal Computer Architect at MIPS
Contributor to Verilator (the canonical open-source RTL simulation/linting tool) and has FireSim (FPGA-accelerated hardware simulation) pinned on his SiFive work GitHub account (timsnyder-siv)
MS EE from UW-Madison, BS EE from UT Austin
Based in Austin, TX
Hireability: MEDIUM — strong job-switching history across AMD, Samsung, SiFive, MIPS; no explicit open-to-work signal but demonstrated career mobility across top-tier hardware companies within the transition window

verilator/verilator firesim/firesim

-T

-T.K.-

medium hireability

PhD student@SLICE Lab and Hybrid Robotics at UC Berkeley

Previously: Undergrad student @ University of California, Berkeley

San Francisco, US

Strong RTL relevance: 81 commits to ucb-bar/chipyard (leading open-source RISC-V SoC generator), pinned repos include a RISC-V single-cycle CPU in Verilog/Chisel and ucb-bar/MaDa (FPGA SoC generation framework with Chisel/Verilog)
PhD student at UC Berkeley working at the intersection of hardware and robotics
Based in Berkeley, CA (US — passes hard requirement)
Hireability: MEDIUM — confirmed PhD student at UC Berkeley; no graduation timeline or 'open to work' signals found; no recent CV or website activity in last 180 days. Worth reaching out to understand timeline

ucb-bar/chipyard T-K-233/RISC-V-Single-Cycle-CPU ucb-bar/MaDa

Trevor McKay

medium hireability

Strong match: Hardware Engineer at SiFive (premier RISC-V IP company), 27 contributions to chipsalliance/chisel, pinned chisel + circt repos confirm deep RTL/Chisel/CIRCT expertise
US-based in San Francisco
Top-1% for RTL/Chisel at their experience level
Passes all hard rejection checks (not a professor, founder, or consultant)
Decision: Qualify

trmckay/chisel trmckay/circt chipsalliance/chisel

Wei-Lun Chiu

medium hireability

EDA engineer at Cadence Design Systems (San Jose, CA), MSECE from CMU
Pinned verilator fork (SystemVerilog simulator) as top repo with 2 commits to upstream verilator/verilator; bio explicitly claims 'EDA expert with top conference pubs' — web search corroborates DAC and ICCAD publications
Strong RTL/SystemVerilog signal with direct EDA tool development experience
Hireability: MEDIUM — employee at Cadence (a large company, not self-founded); GitHub account active as recently as Dec 2025 but no explicit open-to-work signal; likely 3-5 years into role given account age (Jan 2020), within typical transition window

verilator/verilator weilun-chiu/verilator

Wesley W. Terpstra

medium hireability

Passes all hard rejection rules (not a professor, founder, CEO, or consultant)
US-based
Strong RTL credentials spanning VHDL, Verilog, and Chisel with direct RISC-V ASIC/SoC development at SiFive (HiFive1)
Qualifies under Strong relevance + Medium hireability

IEEE Xplore publications — hardware/timing systems (GSI/CERN)opa — Open Processor Architecture (VHDL)gn4124-core — Genum 4124 core (Verilog)pcie-wb — PCIe-Wishbone linux kernel driver chipsalliance/chisel — 5 contributions to canonical Chisel RTL repo

William D. Jones

medium hireability

Qualified: US-based (NJ), strong RTL skills across Verilog and Amaranth HDL, formal verification experience (yosys/sby), open-source RISC-V CPU and FPGA design work, silicon die analysis, contributions to verilator and openFPGALoader
No professor/founder/CEO flags
Unknown employer but passes all hard rejection rules

sentinel spi_tb ym2151-decap gp4-tests

Zachary Yedidia

medium hireability

Moderate RTL experience (Chisel RISC-V core targeting real FPGAs, 10 commits to chipsalliance/chisel, SystemVerilog teaching guide for Harvard digital design course) combined with medium hireability (active Stanford PhD student ~1.5 years from graduation) meets the qualify threshold
Primary research is systems/security, not RTL-first, so outreach should angle toward hardware-adjacent roles or roles that value compilers + hardware cross-skills

Lightweight Fault Isolation: Practical, Efficient, and Secure Software Sandboxing (ASPLOS 2024)Deterministic Client: Enforcing Determinism on Untrusted Machine Code (OSDI 2025)riscinator chisel3 (fork)

@VidyaChhabria

low hireability

Qualified despite low
hireability: strong RTL/EDA signal (Decision Matrix: Strong + Low = Qualify with note). Tenure-track faculty; very unlikely to leave academia in the near term

OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education OpeNPDN: ML-based Power Delivery Network Synthesis and Optimization ThermEDGe/IREDGe: Encoder-decoder generative networks for thermal/IR analysis The-OpenROAD-Project/OpenROAD VidyaChhabria/OpeNPDN VidyaChhabria/OpenROAD-flow-scripts

Abraham Gonzalez

low hireability

Strong RTL match (Chipyard, FireSim, BOOM, Chisel/Scala, RISC-V SoC design, pre-silicon testing, FPGA simulation) but low hireability due to being a very new hire at Google (~Oct 2025)
No open-to-work signals
Per decision matrix: Strong relevance + Low hireability → Qualify with timing note

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs (IEEE Micro 2021)PhD Dissertation: Hyperscale Cloud Data Center Architectures, Accelerator Scheduling, and Agile Hardware Design (UC Berkeley 2025)ucb-bar/chipyard firesim/firesim riscv-boom/riscv-boom abejgonzalez/firesim abejgonzalez/firechip

andy fox

low hireability

Strong RTL/EDA profile with 436 contributions to OpenROAD (RTL-to-GDSII), Verilog/FPGA repos, logic synthesis tools (ABC), and static timing analysis (OpenSTA_parallax)
US-based in Santa Cruz, CA
Hireability is low due to sole proprietor/consultant status with no job-seeking signals detected

The-OpenROAD-Project/OpenROAD andyfox-rushc/verilog-ethernet andyfox-rushc/abc

Austin Rovinski

low hireability

Qualifies on technical strength — top-tier RTL/EDA expertise, OpenROAD founding contributor, active VLSI/chip design research
Hireability is LOW per decision matrix (Strong + Low → Qualify with note)
Tenure-track faculty at NYU since Fall 2023, showing no transition signals

Accelerating Detailed Routing Convergence through Offline Reinforcement Learning Towards Free, Open, and Ubiquitous Hardware Design (PhD Dissertation)A Shared Memory Parallel Implementation of the RePlAce Global Cell Placer (VLSID 2020)rovinski/OpenROAD The-OpenROAD-Project/OpenROAD rovinski/FreePDK45_for_KLayout

Cho Moon

low hireability

Strong RTL/EDA background with direct OpenROAD authorship qualifies on topic
Per decision matrix Strong + Low = Qualify (with note)
Qualified with low hireability caveat

The-OpenROAD-Project/OpenROAD precisionmoon/OpenSTA

Howard Mao

low hireability

Top-1% RTL/Chisel/RISC-V engineer with Berkeley pedigree and direct contributions to canonical open-source chip infrastructure (Rocket Chip, FireSim, Chipyard)
Qualified despite low hireability due to exceptional technical depth

The Rocket Chip Generator FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud An Agile Approach to Building RISC-V Microprocessors (IEEE Micro, 2016)chisel-float riscv-dma3 ez8 rocket-chip firesim

Jack Koenig

low hireability

Strong match on RTL/hardware compiler expertise (Chisel/FIRRTL/CircuitIR maintainer, RISC-V/ASIC toolchain)
US-based
Qualified despite Low hireability because the technical profile is top 1% and warrants outreach per the Strong+Low rule

Automated Testing, Verification and Repair of RTL Hardware Designs chipsalliance/chisel chipsalliance/firrtl

Jerry Zhao

low hireability

Top-1% RTL profile: PhD-level expertise in Chisel RTL design, RISC-V microarchitecture (OOO cores, vector units, NoC, SoC), and ASIC methodology from Berkeley ADEPT/ASPIRE labs
Qualifies on topic strength alone (Strong relevance)
Hireability is LOW (new hire at OpenAI <1yr, high-prestige role), but Strong+Low decision matrix says Qualify with note

Constellation: An Open-Source SoC-Capable NoC Generator ucb-bar/chipyard riscv-boom/riscv-boom ucb-bar/constellation chipsalliance/rocket-chip ucb-bar/saturn-vectors riscv-software-src/riscv-isa-sim

Jim Lawson

low hireability

Strong RTL/Chisel/FIRRTL expertise — core contributor to chipsalliance/chisel ecosystem and co-author of FIRRTL spec paper
US-based (Berkeley, CA)
Qualified despite low hireability due to exceptional topic relevance (Strong + Low per decision matrix: Qualify with note)
Note: long-tenure academic staff, likely not actively seeking industry roles

Reusability is FIRRTL Ground: Hardware Construction Languages, Compiler Frameworks, and Transformations chipsalliance/chisel ucbjrl/chisel-torture ucbjrl/vcd2step

Kevin Kiningham

low hireability

Strong RTL/ASIC background: Stanford EE PhD, authored SystemVerilog/Verilog ASIC design tutorials (kkiningh/asic-design, ~91% HDL), built rules_verilator (Bazel integration for Verilator), contributed to verilator/verilator, and designed a hardware CNN accelerator in Verilog
Currently Member of Technical Staff at Anthropic (joined Jan 2024)
US-based (San Francisco)
Hireability: LOW — joined Anthropic ~14 months ago, still early in that role

Design and Analysis of a Hardware CNN Accelerator kkiningh/asic-design kkiningh/rules_verilator verilator/verilator

Matt Guthaus

low hireability

Exceptionally strong RTL/VLSI/EDA profile: creator of OpenRAM (open-source SRAM compiler in Verilog/Python) and lead contributor to OpenROAD RTL-to-GDS flow (74 commits)
PI of VLSI Design and Automation Lab at UCSC; work spans physical design, EDA tooling, low-power circuits, and open-source chip flows
Pinned repos confirm active Verilog/RTL-to-GDS work
US-based (Santa Cruz, CA)
Hireability: LOW — tenured professor at UCSC since ~2001, no signals of departure. Had a prior Google visiting faculty / Staff Research Scientist stint showing some industry openness, but is back at UCSC and presenting at ORConf 2025. Qualifies per decision matrix (Strong + Low → Qualify, note low hireability)

mguthaus/OpenRAM The-OpenROAD-Project/OpenROAD mguthaus/OpenROAD-flow-scripts

Nicolas Brunie

low hireability

Strong RTL/hardware relevance (FPU micro-architect, Chisel contributor, CIRCT hardware compiler work, RISC-V vector/crypto) + US-based at SiFive Santa Clara
Hireability low due to ~5yr SiFive tenure, leadership role, and no open-to-work signal, but technical profile is top-1% for this search — recommend outreach

circt (fork)rvv-keccak floatConverter riscv-v-spec (fork)riscv-bitmanip (fork)riscv-crypto (fork)

Palmer Dabbelt

low hireability

Top-1% RTL/RISC-V candidate: Architecture/RTL lead on two tapeout processors, original RISC-V Linux kernel maintainer, Chisel/Rocket Chip contributor, 15+ years spanning hardware and systems software
US-based (Redwood City, CA)
Decision matrix: Strong relevance + Low hireability → Qualify with note
Currently at Meta, no open-to-work signals

palmer-dabbelt/rocket-ecc palmer-dabbelt/cisc-v palmer-dabbelt/vcddiff

Paul Rigge

low hireability

Strong RTL/hardware match: PhD-level Chisel + FIRRTL + RISC-V expertise, active contributor to core open-source hardware stack, currently doing hardware synthesis work at Google
Qualified despite low hireability because profile strength is exceptional and long-tenure candidates at Google are still worth a reach-out for top-tier RTL roles

chipsalliance/chisel chipsalliance/firrtl chipsalliance/rocket-chip ucb-bar/dsptools google/xls freechipsproject/chisel-bootcamp

Richard Lin

low hireability

Qualified despite low
hireability: Richard Lin is one of the most directly relevant RTL/HDL tooling researchers in this search — PhD-level, Chisel contributor, chisualizer author, HDL compiler researcher. Worth keeping on file even if timing is poor

Weaving Schematics and Code: Interactive Visual Editing for Hardware Description Languages (UIST '21)Polymorphic Blocks: Unifying High-level Specification and Low-level Control for Circuit Board Design (UIST '20)Computational Support for Multiplicity in Hierarchical Electronics Design (SCF '22)chipsalliance/chisel ducky64/chisualizer BerkeleyHCI/PolymorphicBlocks

Tom Spyrou

low hireability

Chief Architect of OpenROAD (507 commits to The-OpenROAD-Project/OpenROAD), the leading open-source autonomous RTL-to-GDSII implementation flow. 30+ years EDA expertise spanning RTL synthesis, STA, ASIC physical design, FPGA compilers (Intel Quartus), and power grid analysis
Has led landmark EDA tools: PrimeTime, Voltage Storm, First Encounter, Open Access Database
Pinned repos include OpenLane (RTL-to-GDSII flow, Verilog) and DREAMPlace (deep-learning VLSI placement, C++)
San Diego, CA — US requirement satisfied
Hireability: LOW — founder-CEO of Precision Innovations Inc (est. 2019), the primary industrial developer and commercial support entity for OpenROAD. No open-to-work signals found; GitHub bio and profile unchanged; no LinkedIn activity indicating departure. Deeply anchored as company founder. Worth a senior reach-out given unmatched open-source EDA seniority

The OpenROAD Project: Unleashing Hardware Innovation OpenROAD: Toward a Self-Driving, Open-Source Digital Implementation Flow The-OpenROAD-Project/OpenROAD tspyrou/OpenLane tspyrou/DREAMPlace

Runs

#1completed70 qualified / 81 foundMar 30, 8:34 AM